1. Field of the Invention
This invention generally relates to a signal sampling apparatus and a method, and more particularly to a signal sampling apparatus and a method for a DRAM memory.
2. Description of the Related Art
FIG. 1 shows a schematic view of a conventional memory controller 10 coupled to a double data rate (DDR) memory 12. The memory controller 10 utilizes a bi-directional data strobe signal DQS to write a plurality of data signals DQ0 to DQn into the DDR memory 12 or read out the plurality of data signals DQ0 to DQn from the DDR memory 12.
In DDR memory standard, the DDR memory 12 can sample data from the data signals DQ0 to DQn at each rising and falling edge of the data strobe signal DQS. Therefore, each rising edge and each falling edge of the data strobe signal DQS should occur while each of the data signals DQ0 to DQn is steady within a data valid window so that the data of the data signals DQ0 to DQn can be properly sampled.
Ideally, as shown in FIG. 2, the valid time T (e.g. time t1 to t2) of the data valid window for each of the data signals DQ0 to DQn is fixed while the rising edge 14 and the falling edge 16 of the data strobe signal DQS respectively occur within the valid time T of two adjacent data valid windows (only one shown in FIG. 2), and furthermore, while occurs at the middle of the valid time T. For example, the rising edge 14 of the data strobe signal DQS occurs at the middle of the valid time T between the time t1 to t2. However, practically, when the memory controller 10 and the DDR memory 12 are disposed on a circuit board (not shown), the conducting lines printed on the circuit board for transmitting the data signals DQ0 to DQn usually have different lengths due to circuit layout design, which may cause skews occurring between the data signals DQ0 to DQn and thus result in the data valid window for each data signal to have different valid time as shown in FIG. 3.
As shown in FIG. 3, the valid time T1 (i.e. time t1 to t4) of the data valid window for the data signal DQ2 is the longest, and the valid time T2 (i.e. time t2 to t3) of the data valid window for the data signal DQn is the shortest among those for the data signals DQ0 to DQn. In order to properly sample all of data from the data signals DQ0 to DQn, the rising edge 14 of the data strobe signal DQS is limited to occur within the shortest valid time T2. In particular, when the data transmitting speed is increased between the memory controller 10 and the DDR memory 12, the above-mentioned limitation will cause the valid time or the timing margin of the data valid window to be insufficient.
Accordingly, the present invention provides a signal sampling apparatus and method for a DRAM memory whereby solving the above-mentioned problems in the prior art.